IC Reverse Engineering Analyze

For IC extraction and circuit analysis, we developed ten sets of software to dedicated improving the accuracy and reverse engineering capacity for every steps.

 
   

IcImagePicker

Set of Leica optical microscope acquisition system, to support the 0.25um above process technology to take pictures and size measurement.

 

SemPicker

SEM Electron Microscope acquisition system to support high-end process technology 180nm following camera and size measurement.

 

IcImageFitting

Provides massive IC chip seamless images of  the same layers, precise alignment of different layers and image packed functionality.

The main function   The main function   The main function
  • Manual camera: Good human-computer interaction, a key acquisition.
  • Automatic camera: Automatically calculates the focus to complete the acquisition.
  • Quality the moving image, accurate and moving image.
  • High flexibility collection methods.
  • Automatically calculate the row and column number. Access to acquisition of the number of sheets.
  • The ranks of positioning, to quickly locate a single image.
  • Automatic exposure and white balance, fast focus.
 
  • Auto-focus camera, without human intervention to complete acquisition.
  • Designated collection area to enhance the flexibility of the acquisition
  • Quantify the moving image, accurate and moving image.
  • Automatically calculate the row and column number.
  • The ranks of positioning, to quickly locate a single image.
  • Automatic exposure and white balance, fast focus.
 
  • Supports automatic stitching of the same layer, optimize stitching, automatic correction and automatic alignment of different layers.
  • Support image rotation, scaling and multi-window display.
  • Support the entire map export and regional export, improve the flexibility of export.
  • Professional and friendly man-machine interface.
  • Support the commonly used image formats of JPG, BMP, GIF, PNG
  • Support hundreds of G images capacity.
  • Splicing error: within half a hole
         
Technical Specifications   Technical Specifications    
  • Image resolution: 2556 X 1916
  • Image storage format: JPEG
  • Measurement of dimensional accuracy: 0.001mm
  • Average photographed rate of: 3 sec/pic
  • Average daily volume collection: 5000 above
  • Support stage: Leica INM100, DM4000-6000, Prior
  • Support CCD: QImaging, Pixera
 
  • Image resolution: 5120×3840
  • Image storage: JPEG
  • Measurement of dimensional accuracy: 0.001um
  • Average photographed rate of: 26 sec/pic
  • Average daily volume collection: 5000 above
  • Support SEM: JEOL7001F JEOL6700F
   

 

IC Circuit Analysis Redesign System
 
   

NetEditor

Extraction of digital and analog circuit netlist data and export standard Edif200, Verilog netlist data.

 

 

NetEditorLite

Extraction of digital and analog circuit netlist data and export standard Edif200, Verilog netlist data.

 

LayoutEditor

Layout data to extract the digital circuits and analog circuits and export standard CIF layout data.

The Main Function   The Main Function   The Main Function
  • Efficient image display technology, massive IC photos can be displayed within 0.1 seconds
  • Multi-user collaborative work, faster
  • Efficient, practical identification algorithm, the correct rate of 95% savings in manpower, but also makes the extraction rate increased tenfold or even a hundred times, especially for large digital circuits
  • Algorithm to the images do not ask, adaptable
  • ERC check and SVS contrast.
  • Export the Verilog ,Edif200
  • Support the one million level circuit extraction.
 
  • Using caching technology to display a IC background image, the image can be made to support a hundred G image within tens of milliseconds to refresh the display accordingly
  • ERC check
  • SVS contrast
  • Supports export standard Verilog, Edif200 format
  • The stand-alone version, can be break away from the server is running
 
  • Efficient image display technology, massive IC photos can be displayed within 0.1 seconds
  • Efficient, practical identification algorithm(Line network may be automatic identification, unit have 8 kinds of state may be automatic search), the correct rate of 95% savings in manpower, but also makes the extraction rate increased tenfold or even a hundred times, especially for large digital circuits.
  • Algorithm to the images do not ask, adaptable
  • Support real-time DRC or global DRC and the corresponding error report.
  • Export standard GDSII, can be directly imported into the Cadence
  • Multi-user collaborative work, faster
  • Support the one million level circuit extraction

 

The Main Feature Comparison

  NetEditorLite NetEditor LayoutEditor
Multi-User Co-operation No Yes Yes
Routes Automatic Identification No Yes Yes
Cell Automatic Identification No Yes Yes
ERC Yes Yes No
DRC No No Yes
SVS Yes Yes No
Export Format Edif200,Verilog Edif200,Verilog CIF
Running w/o Server Yes No No

 

 

ChipDataSvr

C / S distributed database, to provide one million magnitude of IC design data, realization of design teams work together seamlessly, thereby greatly enhancing the efficiency of VLSI design.