IC Reverse Engineering Service

With powerful self-developed IC reverse engineering software and advanced SEM/OM equipment as well as a technically specialized circuit analysis engineering team, SIPTK is able to provide the best IC reverse engineering service at differential level of service requirement from chip to circuit equation. 

Circuit Analysis
 

Customized CA

  • Group related devices to form basic subcircuit block.
  • Identify circuit block function.
  • Identify input/output signal type and properties.
  • Critical physical design note
  • Principle of circuit operation
  • Equations of critical output
 

Selected CA

  • Sensor
  • Power
  • RF
  • Interface
  • Driver
  • Data Converter
  • Clock and timing
  • Analog modules
 

ROM code extraction

 

Customized Circuit Analysis
 

CA for patent service

  • Identify signal property
  • Identify circuit block function
 

CA for design reference

  • Basic digital cells
  • Basic analog module
  • Major circuit function formed by analog modules and passive devices
  • Circuit operation
  • Input/output equations
 

MCU firmware reverse

  • Mask ROM, flash, and OTP, etc...

 

Reverse Engineering Procedure
  • Power domain trace
  • Circuit block marking
  • Device identification and parameter measurement
  • Basic circuit block and hierarchical re-organization
 
  • Functional block identification and signal net labeling
  • Description of circuit operation
  • Circuit equation

Basic RE

  • Power domain trace
  • Block definition by guard ring
  • Device identification
  • Device parameter measurement
  • Automatic net labeling
  • Circuit extraction

 

Basic circuit block and hierarchical re-organization

  • Amplifier, bias, comparator, logic gates, flip-flop
 

Analog/digital circuit module identification

  • Bandgap, LDO (Low Dropout Regulator), V-to-I, charge pump, oscillator, PGA
  • counter, shift register, adder, level shifter
  • IO buffer, ESD (Electrostatic Discharge)
 

Major functional block re-organization and verification

  • Top level re-partition as datasheet description
  • IO labeling
   

 

Design Support
 

Start-up support

  • Design environment setup
  • Design flow establishment
  • Signoff check item documentation
  • Design training
 

Front end support

  • Design to meet spec
  • Design for better performance
  • FPGA verification
 

Back-end support

  • Full customer layout
  • APR
  • DRC/LVS verification
  • XRC post simulation
  • Tape out support
 

ASIC

  • phase out product
  • High quantity
 

Standard cell/IO library

  • For semi-customized requirement
  • Digital design kit support